`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/06/20 15:53:09
// Design Name: 
// Module Name: sim_DDS
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module sim_DDS(

    );
    reg clk;
    reg clk_160M;
    reg rst_n;
    reg PPS_ref;
    reg [31:0] control_offset;
    reg [31:0] Fword;
    wire clk10M;
    wire PPS1;
    wire PPS2;
    

    
    initial begin
        clk = 1'b0;
        clk_160M = 1'b0;
        rst_n = 1'b0;
        PPS_ref = 1'b0;
        Fword = 32'd0;
        #100
        rst_n = 1'b1;
        #100
         Fword = 32'hFFFFFFFF;
        #1000
        Fword = 32'h00000002;
        #1000
        PPS_ref = 1'b1;

    end

    Sync_10M u10M(
    .clk_40M(clk),
    .clk_160M(clk_160M),
    .rst_n(rst_n),
    .PPS_ref(PPS_ref),
    .Fword(Fword),
    .clk10M(clk10M),
    .PPS_10M(PPS1),
    .PPS_trigger(PPS2)
    );

    always #12.5 clk = ~clk;
    always #3.125 clk_160M = ~clk_160M;
    
endmodule
